digital logic and design mcqs

Digital Logic and Design Important MCQs for LCC

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Digital Logic and Design MCQs (Part-1)

  • The characteristic feature of an asynchronous sequential circuit is                    . (Feedback path)
  • The                      is an example of an asynchronous sequential circuit.  (Ripple counter)
  •                     type of flip-flop is commonly used in asynchronous sequential circuits. (SR flip-flop)
  • The primary disadvantage of asynchronous sequential circuits is                    . (Susceptibility to hazards)
  • The main advantage of asynchronous sequential circuits over synchronous sequential circuits is                    .  (Lower power consumption)
  •                     hazard occurs when there is a temporary glitch in the output due to a change in the inputs.  (Dynamic hazard)
  • The hazards in asynchronous sequential circuits can be eliminated by                    .(Adding delay elements)
  • The purpose of a hazard cover in an asynchronous sequential circuit is                    . (To eliminate hazards)
  •                     hazard occurs when the output momentarily transitions to an incorrect value before settling to the correct value.  (Static hazard)
  • The critical race condition in asynchronous sequential circuits is                    . (When two or more flip-flops change state simultaneously)
  •                     is not a method to overcome race conditions in asynchronous sequential circuits.   (Utilizing edge-triggered flip-flops)
  •                     type of flip-flop is more prone to race conditions in asynchronous sequential circuits.  (Master-slave flip-flop)
  • The purpose of a state assignment in asynchronous sequential circuits is                    . (To minimize the number of states)
  •                     is an example of an asynchronous sequential circuit application. (Memory)
  • The stability of asynchronous sequential circuits can be ensured                    . (By avoiding combinational loops)
  • The purpose of a register file in a processor is                    (To store data)
  • The storage capacity of a register is determined by                   .  (The number of flip-flops used)
  • The operation performed by a shift register is                   . (Shifting of data)
  • A universal shift register can perform the following operations                    . ( Shift left, Shift right, Parallel load)
  • The purpose of a counter register is                    .  (To count the number of clock cycles)

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Digital Logic and Design MCQs (Part-2)

  • The difference between a serial-in, serial-out (SISO) shift register and a parallel-in, parallel-out (PIPO) shift register is                    .  (SISO shift register can shift data in one direction, while PIPO shift register can shift data in both directions)
  • The purpose of a parallel load operation in a register is                    . (To load data into the register in parallel)
  • The role of a special-purpose register, such as the Program Counter (PC), is                    .  ( To hold the current instruction being executed)
  • The typical size of a general-purpose register in a computer system is                    . (32 bits or more)
  • The readability of a register refers to its ability to                    . (Be accessed and read by other components)
  • The purpose of a register file in a processor is                    . (To store data)
  • The operation performed by an accumulator register is                    . (Arithmetic and logical operations)
  • The primary advantage of using registers in a processor is                    . (Faster data access and manipulation)
  • The purpose of a stack pointer register in a processor is                    . ( To manage the memory stack for function calls)
  • The stability of a register refers to its ability to                    . (Store data without errors or loss)
  • The flip-flop in digital logic design is                    .  (A temporary storage device)
  • The master-slave flip-flop is composed of                    .  ( Two SR flip-flops)
  • The clock signal in a flip-flop is used to                    .  (Synchronize the operation of the flip-flop)
  • The input combination that triggers a positive-edge triggered D flip-flop is                     (D = 0, CLK = 1)
  • The characteristic table of a D flip-flop represents                    ( The relationship between the input and output of the flip-flop)
  • The flip-flop that eliminates the possibility of a “race condition” is                    . ( JK flip-flop)
  • The output of a flip-flop is affected by the clock signal during the                    (Setup time)

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Digital Logic and Design MCQs (Part-3)

  • The flip-flop that can act as a frequency divider is                    .  ( T flip-flop)
  • The input combination that triggers a negative-edge triggered JK flip-flop is                    .  (J = 0, K = 1, CLK = 0)
  • The flip-flop that can store multiple bits of information is                    .  (JK flip-flop)
  • The input combination that triggers a positive-edge triggered SR flip-flop is                    .   (S = 1, R = 0, CLK = 1)
  • The flip-flop that can toggle its output is                    .   (T flip-flop)
  • The input combination that triggers a negative-edge triggered D flip-flop is                    .   (D = 1, CLK = 0)
  • The flip-flop that can be used to implement a counter is                    .  (JK flip-flop)
  • The input combination that triggers a positive-edge triggered JK flip-flop to toggle its output is                    .   ( J = 1, K = 0, CLK = 1)
  • The multiplexer is                    .  (A device that combines multiple inputs into a single output)
  • The number of selection lines required for an n-to-1 multiplexer is                    (2n)
  • The input lines of a multiplexer are also known as                    .  (Data lines)
  • The output of a multiplexer is determined by                    .   ( The control inputs)
  • The demultiplexer is                    .   (A device that splits a single input into multiple outputs)
  • The number of selection lines required for a 1-to-n demultiplexer is                    . ( 2n)
  • The control lines of a demultiplexer are used to                    .  (Select the output line)
  • The function of a multiplexer can be described by                    .  (Truth table)
  • The function of a demultiplexer can be described by                    .  (Boolean expression)
  • The number of output lines in a multiplexer is determined by                    (The number of selection lines)
  • The multiplexer can be used to implement                     (Encoders)
  • The demultiplexer can be used to implement                    .  (Decoders)
  • The number of output lines in a demultiplexer is determined by                    ( The number of data inputs)
  • The multiplexer with 2 selection lines can select between                    .  ( 4 data inputs)
  • The demultiplexer with 3 selection lines can distribute the input to                    .  (8 output lines)
  • Latches in digital logic design are                    .  (Sequential logic circuits)
  • The latch that is level-sensitive and requires a level change in the enable input to change its state is                    (D latch)

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Digital Logic and Design MCQs (Part-4)

  • The type of latch that has two stable states and can be used for storing one bit of data is                    .  (SR latch)
  • The input combination that causes a transparent latch to store the input data is                    . (Enable = 1, Input = 1)
  • The latch that has two inputs, a data input, and a control input, is                    . ( D latch)
  • The input combination that causes an SR latch to be in an invalid state is                    . (S = 1, R = 1)
  • The latch that can be used to eliminate the invalid state of the SR latch is                    .  ( JK latch)
  • The characteristic table of a latch represents                    . ( The relationship between the input and output of the latch)
  • The input combination that causes a JK latch to toggle its output is                    . ( J = 1, K = 1)
  • The latch that requires a clock signal to change its state is                    . (JK latch)
  • The input combination that causes a T latch to toggle its output is                    .  (T = 0, CLK = 1)
  • The latch that can store multiple bits of information is                    . (JK latch)
  • The latch that can be used to implement a frequency divider is                    . (T latch)
  • The input combination that causes an SR latch to hold its state is                    . (S = 0, R = 0)
  • The latch that can be used as a building block for more complex sequential circuits is                    .  (SR latch)
  • The memory hierarchy is                    . (A technique for organizing computer memory)
  • The main purpose of the memory hierarchy is to                   .  (Reduce the access time of the memory)
  • The memory level that provides the fastest access time but has the smallest capacity in the memory hierarchy is                    .  (Cache memory)
  • The memory level that provides a compromise between access time and capacity in the memory hierarchy is                    .  (Primary memory)
  • The memory level that provides the largest capacity but has the slowest access time in the memory hierarchy is                    .  (Secondary memory)
  • The memory level that is typically used for long-term storage and is non-volatile in the memory hierarchy is                    (Secondary memory)
  • The memory level that is used to extend the capacity of primary memory and is smaller and faster than secondary memory in the memory hierarchy is                    . (Cache memory)
  • The memory level that is typically used for backup and archival purposes in the memory hierarchy is                    .  (Tertiary memory)
  • The memory level that is directly accessed by the CPU and stores instructions and data during program execution in the memory hierarchy is                    . (Primary memory)
  • The memory level that is closest to the CPU and holds frequently accessed data and instructions in the memory hierarchy is                    . (Cache memory)
  • The concept of the memory hierarchy is based on the principle of                    . (Locality of reference)
  • The process of transferring data between different levels of the memory hierarchy is known as                    . (Memory swapping)
  • The memory level that is most expensive per unit of storage in the memory hierarchy is                    . (Primary memory)

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Digital Logic and Design MCQs (Part-5)

  • The memory level that is the least expensive per unit of storage in the memory hierarchy is                    (Secondary memory)
  • The memory hierarchy is designed to optimize                    .  (Storage capacity, Access time, Cost)
  • A combinational circuit is                    .   (A circuit whose output depends only on the current input)
  • The basic building blocks of combinational circuits are                     (Gates)
  • The output of a combinational circuit is determined by                    .   (Current input only)
  • Combinational circuits are used for                    .  (Logic operations)
  • The logical operation performed by an AND gate is                     ( Boolean multiplication)
  • The logical operation performed by an OR gate is                    .   (Boolean addition)
  • The logical operation performed by an XOR gate is                    .  (Exclusive OR)
  • The logical operation performed by a NOT gate is                    .   (Boolean complementation)
  • A half-adder is a combinational circuit that can                     ( Perform addition of two binary numbers)
  • A full-adder is a combinational circuit that can                    .  (Perform addition of two binary numbers)
  • A decoder is a combinational circuit that can                    .  (Convert a binary code into a decimal code)
  • An encoder is a combinational circuit that can                    .   (Convert a decimal code into a binary code)
  • A multiplexer (MUX) is a combinational circuit that can                    .  (Select one of many inputs based on a control signal)
  • A demultiplexer (DEMUX) is a combinational circuit that can                    (Distribute one input to multiple outputs based on a control signal)
  • A comparator is a combinational circuit that can                    .  ( Determine the equality or inequality of two binary numbers)

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